Well known are RAMs which have at least one address port and include storage elements (core cells). In a paper by A. L. Silburt et al entitled "A 180-MHz 0.8-.mu.m BiCMOS Modular Memory Family of DRAM and Multiport SRAM", IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, March 1993, p. 222, at 227 shows various arrays of RAM storage elements.
In RAMs, a problem is to develop a practical, non-intrusive method for sensitizing shorts between bit lines from different ports. In a paper by B. Nadeau-Dostie et al entitled "Serial Interfacing for Embedded-Memory Testing", IEEE Design & Test of Computers, April 1990, p. 52 discloses BIST (built-in self test) architecture and memory test.
Detection of shorts due to manufacturing defects between bit lines from different ports which run parallel to each other over large distances (the "height" of the memory array) is difficult due to the small differential signal swing used in high-speed memory port architectures. Shorts between word lines from different ports are likewise difficult to detect without special test algorithms. Such faults may pass undetected by conventional BIST or functional testing means during manufacturing test and result in intermittent failures in the field. A shadow write methodology may be used to sensitize the port-to-port bit line and word line short failures during BIST or functional testing.